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Silicon Sprint AUC Workshop
Silicon Sprint AUC Workshop

Workshop Modules

  • Module 0: Installation & Environment Setup
  • Module 1: LibreLane Flow & Execution to PDN
  • Module 2: Placement, CTS & Timing Optimization
  • Module 3: Routing and Physical Optimization
  • Module 4: Physical Signoff
  • Module 5: Caravel User Project Wrapper Integration
  • Module 6: Hardening Your Design for the OpenFrame Multi-Project
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Index

C | D | E | F | G | I | L | P | R | S | T | W

C

  • clock skew
  • CTS, [1], [2]

D

  • DEF
  • DRC, [1], [2], [3], [4], [5], [6]
  • DRT

E

  • EDA

F

  • flip-flop

G

  • GDSII, [1], [2], [3], [4]
  • GPIO
  • GRT

I

  • I/O

L

  • LEF, [1], [2], [3]
  • LVS, [1], [2], [3], [4]

P

  • PDK
  • PDN, [1], [2], [3], [4], [5]
  • PnR, [1], [2], [3], [4]
  • PPA, [1], [2]
  • PVT, [1]

R

  • RTL

S

  • SDC, [1], [2], [3], [4], [5], [6]
  • SPEF
  • SPICE, [1], [2]
  • STA, [1], [2], [3], [4], [5], [6]

T

  • timing closure
  • TNS, [1], [2], [3]

W

  • WNS, [1], [2], [3], [4]
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