Silicon Sprint — AUC ASIC Design Workshop¶

About This Workshop

A hands-on journey from RTL to silicon — hardening an AES-128 Accelerator with the open-source LibreLane toolchain on the SkyWater 130nm process node.

What You Will Build¶

An AES-128 encryption core wrapped in a Wishbone bus interface (aes_wb_wrapper), integrated into the Caravel SoC harness and taken all the way to a verified, manufacturable GDSII layout.

Stage	Tool
RTL Linting & Synthesis	Yosys / Verilator
Floorplan & Power Network	OpenROAD
Placement & Clock Tree Synthesis	OpenROAD
Routing	OpenROAD / TritonRoute
Physical Signoff (DRC · LVS · GDSII)	Magic / KLayout / Netgen

Modules¶

Workshop Modules

Module 0 — Environment Setup

Nix installation, LibreLane setup, repository cloning, and environment verification.

Start here before anything else.

Module 0: Installation & Environment Setup

Module 1 — RTL Integration & ASIC Flow

Wishbone wrapper integration, synthesis exploration, floorplan, and PDN generation.

Requires Module 0.

Module 1: LibreLane Flow & Execution to PDN

Module 2 — Placement & CTS

I/O pin placement, global and detailed placement, Clock Tree Synthesis, and post-CTS timing repair.

Requires Module 1.

Module 2: Placement, CTS & Timing Optimization

Module 3 — Routing

Global routing, antenna repair, post-GRT design repair, and detailed routing with TritonRoute.

Requires Module 2.

Module 3: Routing and Physical Optimization

Module 4 — Physical Signoff

Fill insertion, parasitic extraction, post-PnR STA across 9 corners, IR drop analysis, DRC, LVS, and final GDSII generation.

Requires Module 3.

Module 4: Physical Signoff

Module 5 — Macro-First Hardening strategy

Hardening the aes core with the Wishbone wrapper as a macro

completed full physical signoff in Module 4 and that the classic_flow_eco

Module 5: Caravel User Project Wrapper Integration

Module 6 — OpenFrame Multi-Project Chip

Hardening Your Design for the OpenFrame Multi-Project Chip

Module 6: Hardening Your Design for the OpenFrame Multi-Project

Toolchain¶

Tool	Role
Verilator	RTL linting
LibreLane	RTL-to-GDSII flow orchestrator
Yosys	Synthesis and technology mapping
OpenROAD	Floorplan, placement, CTS, routing, and STA
Magic	Layout editor, DRC, and SPICE extraction
KLayout	GDSII viewer, DRC, and XOR verification
Netgen	LVS netlist comparison
SkyWater 130nm PDK	`sky130_fd_sc_hd` standard cell library

Credits¶

Developed by Basem Hesham
📧 basemhesham159@gmail.com
💼 LinkedIn Profile

GDSII¶: Graphic Database System II. The standard binary layout format delivered to the foundry for fabrication.
PDN¶: Power Distribution Network. The metal grid delivering VDD and GND to every standard cell.
SDC¶: Synopsys Design Constraints. Tcl-based format specifying timing and clocking constraints.
PnR¶: Place and Route. Standard cell placement and signal wire routing.
STA¶: Static Timing Analysis. Exhaustive path-by-path timing verification without simulation.
DRC¶: Design Rule Check. Verification that the layout conforms to foundry manufacturing constraints.
LVS¶: Layout vs. Schematic. Verification that the physical layout matches the logical netlist.
SPICE¶: Simulation Program with Integrated Circuit Emphasis. Analog circuit simulator for layout verification.
PPA¶: Power, Performance, Area. The three primary VLSI optimisation axes.
CTS¶: Clock Tree Synthesis. Building a balanced clock distribution network to minimise skew.